This invention relates to automatic digital in-circuit testing systems. More particularly, the invention relates to a digital in-circuit tester capable of testing high speed logic devices, such as ECL logic.
Prior-art digital in-circuit testers suffer from several disadvantages. Logic designers have discovered that in certain applications, such as computer main frames, etc., a physically large printed circuit board with as many as 3,000 circuit nodes is less expensive to produce and more reliable in operation. With these larger boards, there has been an increase in the mixture of logic families, i.e., TTL, MOS and ECL devices. Designers are becoming increasingly adept at using whatever devices best meet their speed and performance requirements, rather than using just one logic family for the sake of expediency. Because of its exceptionally high speed ECL logic is being used more and more along with the more common TTL and CMOS devices.
The output voltage swing for an ECL logic device is typically between -1.6 v for logic 0 and -0.8 v for a logic 1. Because of the small voltage swing (0.8 v) between logic 0 and logic 1 and their speed, ECL devices are particularly difficult to test. Prior-art testers have been unable to test ECL devices effectively because they cannot provide the proper logic power supplies, nor can they handle ECL's high slew rates and high sensitivity to noise. The amplitudes of signal abberations, such as "ringing" and "overshoot" usually acceptable in testing TTL, are unacceptable for testing ECL devices. A ringing signal which would look like a logic 1 to a TTL device may look like a bit stream to an ECL device.
Three factors which may negatively affect an ECL test are node driver line impedance, power supply interconnection impedance, and slew rate of the drive signal. To understand the affects, consider the following simplified equation for voltage drop across an interconnection path: EQU e=L(di/dt)+iR.
Both components of the equation, i.e., L (di/dt) and iR, affect voltages both on the node-driver line (AB in FIG. 3) and on the power supply current return line (CD in FIG. 3). On the node-driver lines, the DC component (iR) is relatively small because the short path has low resistence. However, the AC component (L di/dt) can be significant. This is especially true in the case of ECL devices where high slew rates make (di/dt) unavoidably large.
On the supply current return path of prior-art testers, the DC effects are most significant because of the long path (CD in FIG. 3(a)) from the device under test to the point where the response is measured. The current (i) is high because the return line is connected to the system ground bus which carries power supply current for the entire board as well as the node driver return currents. The return line therefore has a large iR noise component. This kind of noise is called "ground shift." With 10-gauge copper wire (adequate for most prior-art testers), a typical value of this ground shift is on the order of 400 mv.
With this amount of ground shift, prior-art board testers are still able to test TTL and CMOS, because 400 mv of offset is a small amount compared to the voltage swings of these devices. However, 400 mv of noise is unacceptable for ECL testing because this amount of ground shift is fully half the proper voltage swing. A ground shift this large will yield erroneous test results.
The AC noise component, L (di/dt), causes further problems, "overshoot" and "ringing." This is an especially troublesome problem with the node driver line (AB FIG. 3). Uncontrolled overshoot can actually destroy devices, especially CMOS, and ringing introduces transients that can exceed logic voltage thresholds resulting in false triggerings and incorrect device response measurements.
A further problem of prior-art in-circuit digital testers is the inability to handle multi-logic testing easily. Prior-art in-circuit testers used a power supply and driver/receiver cards configured as shown in FIG. 3 (a). The 0 v and 5 v power supply and logic voltages shown are appropriate for testing most TTL devices. But if a printed circuit board also contains CMOS and/or ECL devices, this configuration will not work. For example, to test a CMOS device operating between 0 and 12 volts, a different power supply would have to be connected to the board, and on most prior-art testers this has necessitated custom rewiring of the system or the bed-of-nails test fixture through which the power is applied to the board. For a CMOS device operating between -5 v and +5 v, two power supplies would have to be used. Most prior-art testers cannot provide two non-zero voltages, even with rewiring. This limitation is even more severe when it comes to testing ECL devices, for here the power supply voltages are not the same as the logic voltages. ECL power supply voltages are -5.2 v and 0 v, while the logic voltages are -1.6 v for logic 0 and -0.8 v for logic 1.
Therefore, it would be advantageous to provide an automatic digital in-circuit tester which is able to minimize both the noise in the test signals as they appear at the nodes of the printed circuit boards and the ground shift due to the board power supply current loops, thereby significantly reducing the kind of test signal distortion that can damage devices, produce false triggering, or create erroneous measurements.